MEMORY_TEST_SIMULATION

FIG 1: Circuit for memory simulation

Note: Link for the multisim file needed for the simulation is provided at the end of the post.

In this part we are going to simulate a RAM (Memory). The Memory shown below has 2k locations (words) each of size 8 bit. 8 bit word size implies a data input and data output of 8 bit denoted as D0-D7 and Q0-Q7 respectively. 2k memory locations implies an address line of 12 bit denoted as A0-A11. There’s a Write Enable (WE) input. The RAM (memory) performs a write operation when WE is high. It performs read operation when WE is low. There’s a Chip Select (CS) input which enables/disables the memory when it is high/low.

FIG 2: Memory

 

FIG 1 provides the circuit setup to simulate the Memory. There’s an 8 item dip switch pack connected to the data input (D0-D7). This switch helps us input data into the memory. There’s a 4 item dip switch pack connected to address input (A0-A3). Note that this setup let us input an address of only 4 bit. This means only 16 out of 2k locations are addressable.Switch is provided for WE and CS. LED outputs are provided so that the status of each section can be determined nicely.

How to Write and Read:

At first turn off the WE switch and turn on the CS switch. To write into the memory simply set the desired bit value in the 8 item dip switch pack connected to D0-D7. Then set the desired address by setting the bit value in the 4 item dip switch pack connected to A0-A3. Then, turn on the WE switch.

To read the data simply provide the desired address by setting the bit value in the 4 bit item dip switch pack connected to A0-A3 and turn off the WE switch.

To disable the Memory, turn off the CS switch.

Link for the multisim file

https://drive.google.com/folderview?id=0B8cy5TgcyxKMX29rUXNzOEp3cFU&usp=sharing

 

Workshop : 8-bit Computer Architecture

Group photo: After the completion of the workshop

Kathamndu University offers Computer Architecture course for students from Computer and Electrical Department. Some knowledge on digital logic is required to understand the underlying principle of Computer Architecture. Computer Architecture is a field in computer science with enormous possibilities.

Highly qualified instructors are there to help students but most of the students somehow find the course very difficult to comprehend. The virtual complexity barrier prevents students to understand the very beautiful and artistic nature of this course.

Senior students in Digital Club have had their difficulties in the same course. Keeping in mind the difficulty faced by students, Digital Club conducted a workshop on 8-bit Computer Architecture. Beneficiary were students from Department of Electrical and Electronics Engineering batch 2013.

The objective of the workshop was to help students design an 8-bit Computer. The workshop focused on the basics of designing like instruction set, type of BUS, opcode etc.

Students who participated in the workshop became confident enough to answer basic design questions. They could in principle design a basic computer.

Digital Club is thankful to the students who participated in the workshop and made it a place for lively interaction. Further we plan to conduct similar workshop with an aim to address immediate academic need of the students.

COMMON BUS SYSTEM

COMMON BUS SYSTEM

NOTE : Multisim Files needed for this setup are provided in a link at end of this post.

We have built a common bus system as shown in above picture. We have used multisim 11.0. All the parts  in the system are custom built. There are pins for 6 registers to connect with the bus. Data Register connects to the input labelled with DRO TO DR7, Accumulator connects to the input ACO-AC7, Instruction Register to IRO-IR7, Program Counter to PCO-PC7, Address Register to ARO-AR7, and we have one set of 8 pack switch connected to the pins MEMO-MEM7. The switch

Instruction Set Architecture

Instruction set refers to the set of Instruction that a computer can perform. As depicted in the above picture Instruction Set is specified by the software and has to be implemented by the hardware. More number of instructions implies greater complexity for the hardware.

Before we jump 

Block Description

BLOCK DESCRIPTION

In the above picture we have a simple description of our computer. In the example, we use an 8 bit instruction ( that resides in Instruction Register ). The 8-bit instruction is decoded using Instruction Decoder and the corresponding signal is transferred into the Timing and Control Signals Unit.

Timing Signals are

Introduction

In Kathmandu University we take a fundamental Course on Computer Architecture. As a part of Mini Project we design a simple computer. Through this website we will relive the project step by step. That is, we will show you how to actually build an 8-bit Computer. However, actual implementation on hardware gets expensive so, we will limit our design on a circuit simulation software called Multisim. Our work will be based on Computer System Architecture by Morris Mano.

In this series we will go through these steps

• Block Description of the computer
• Instruction Set
• Timing Diagram
• Components used
• Assembling different parts
• Simulation

Welcome to Digital Club (Kathmandu University)

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